Sri Samavedam is SVP of CMOS Technologies at imec since Aug 2019. His responsibilities include programs in logic, memory, photonics and 3D integration. Prior to that, he was senior director of technology development at Globalfoundries in Malta, NY, where he led qualification of 14nm FinFET technology and derivatives into volume production and early development of 7nm CMOS.
He began his research career at Motorola in Austin, TX, working on strained silicon, metal gates, high k dielectrics and fully-depleted SOI devices. He holds a Ph.D. in Materials Science and Engineering from MIT and a masters from Purdue University.
Transistor density in chips continues to follow Moore’s law, but the node to node logic performance improvements have slowed down. Memory and power walls limit compute system performance. Future compute systems will increasingly rely on new materials, new device architectures and system technology co-optimization to realize benefits beyond pure density scaling of compute, connect and store technologies. This talk will highlight technology innovations in logic, memory and 3D integration that will enable continued compute systems scaling. With the anticipated semiconductor industry growth in the next decade, we also need collective action to address the carbon footprint of semiconductor manufacturing.