Dr. Amit

Marathe

Google

SoC/Module Technology & Reliability Engineering Head

Amit Marathe earned his M.S. and Ph.D. in Materials Science and Engineering from the University of California, Berkeley in May 1991 and August 1996 respectively. His research work was in the field of high Tc superconductor SQUIDs and Josephson Junction devices for integrated circuits. Amit joined AMD in Sunnyvale CA soon after graduation. At AMD he was leading and managing the Technology & Reliability Development Organization where his group was involved with technology and microprocessor product qualification. In 2009, his Organization transitioned to Global Foundries (GF) where he continued to lead the technology qualification of advanced nodes (16nm FinFETs & beyond) as well as Assembly/Packaging Reliability & Modeling. In 2011, Amit joined Microsoft and was managing the Silicon/Packaging Operations & Reliability Org for all of Microsoft Hardware. While at Microsoft, his group was responsible for quality & reliability of all custom and off the shelf silicon products in various configurations Amit joined X – Alphabet in 2016 in the Central X Supplier Development Org. In addition to developing new Suppliers & technologies to enable moonshots, he also led the silicon/packaging quality & reliability activities and supplier interface for all projects within X. Soon after, he moved to main Google where he is managing the SOC/Module Technology and Reliability Engineering team supporting all projects across Hardware Programs in Google. He has co-authored over 40 technical research publications as well as a chapter in a book on Moore’s Law Scaling Reliability Challenges. He has chaired sessions at IRPS Conf. and given keynotes at other International Conferences. He is also a co-inventor of over 15 patents granted and over 50 pending US patents in the area of technology & reliability development.

Amit Marathe earned his M.S. and Ph.D. in Materials Science and Engineering from the University of California, Berkeley in May 1991 and August 1996 respectively. His research work was in the field of high Tc superconductor SQUIDs and Josephson Junction devices for integrated circuits. Amit joined AMD in Sunnyvale CA soon after graduation. At AMD he was leading and managing the Technology & Reliability Development Organization where his group was involved with technology and microprocessor product qualification. In 2009, his Organization transitioned to Global Foundries (GF) where he continued to lead the technology qualification of advanced nodes (16nm FinFETs & beyond) as well as Assembly/Packaging Reliability & Modeling. In 2011, Amit joined Microsoft and was managing the Silicon/Packaging Operations & Reliability Org for all of Microsoft Hardware. While at Microsoft, his group was responsible for quality & reliability of all custom and off the shelf silicon products in various configurations Amit joined X – Alphabet in 2016 in the Central X Supplier Development Org. In addition to developing new Suppliers & technologies to enable moonshots, he also led the silicon/packaging quality & reliability activities and supplier interface for all projects within X. Soon after, he moved to main Google where he is managing the SOC/Module Technology and Reliability Engineering team supporting all projects across Hardware Programs in Google. He has co-authored over 40 technical research publications as well as a chapter in a book on Moore’s Law Scaling Reliability Challenges. He has chaired sessions at IRPS Conf. and given keynotes at other International Conferences. He is also a co-inventor of over 15 patents granted and over 50 pending US patents in the area of technology & reliability development.

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Changing Role of Packaging: Opportunities and challenges

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