• Ph. D. Material Science & Engineering, 2001 • Research Faculty Associate, 2004 • TD Engineering Manager, ATTD, Intel Corporation, 2017 • Corporate VP, Head of Package TD Team, TSP (Test & System Package), Samsung Electronics, 2017 ~ present
• Ph. D. Material Science & Engineering, 2001 • Research Faculty Associate, 2004 • TD Engineering Manager, ATTD, Intel Corporation, 2017 • Corporate VP, Head of Package TD Team, TSP (Test & System Package), Samsung Electronics, 2017 ~ present
Moore’s law is still working thru advanced package technology to overcome fab technology limitation. Chipets and heterogeneous integration would be major interesting area for advanced package application. 3D package will be major package in a future and one of key game changers in 3D technology would be gapless hybrid Cu bonding, defining the new boundary between Fab and package process. In order to overcome extremely high interconnect density and heat dissipation issue in memory as well as logic device, package needs to use fab-like process. Samsung advanced package technology including 2.5D and 3D package will be shared and discussed in this forum