Dr. Raghu Chaware has more than 20 years of experience in developing advanced packaging technology for FPGAs and deep experience in Design for Manufacturing, reliability engineering, statistical methods, and yield optimization. He is an Inventor and co-inventor of multiple patents (>20 patents) on industry-leading flip chip and 2.5/3D interconnect packaging technology. He has master’s degree in Material Science from University of Mississippi and Ph.D. in Systems Science and Industrial Engineering from State University of New York at Binghamton (Binghamton University). Currently, he is a Sr. Director at Lattice Semiconductor and leads advanced assembly/packaging development and production teams.
Dr. Raghu Chaware has more than 20 years of experience in developing advanced packaging technology for FPGAs and deep experience in Design for Manufacturing, reliability engineering, statistical methods, and yield optimization. He is an Inventor and co-inventor of multiple patents (>20 patents) on industry-leading flip chip and 2.5/3D interconnect packaging technology. He has master’s degree in Material Science from University of Mississippi and Ph.D. in Systems Science and Industrial Engineering from State University of New York at Binghamton (Binghamton University). Currently, he is a Sr. Director at Lattice Semiconductor and leads advanced assembly/packaging development and production teams.
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