Dr. Subramanian
CHIPS for America R&D Office
Director National Advanced Packaging Manufacturing Program, NIST

Subramanian S. Iyer (Subu) is Director of the National Advanced PackagingManufacturing Program (NAPMP), on assignment from UCLA where he isDistinguished Professor and holds the Charles P. Reames Endowed Chair in theElectrical Engineering Department and a joint appointment in the MaterialsScience and Engineering Department at the University of California at LosAngeles. He is the founding Director of the UCLA Center for HeterogeneousIntegration and Performance Scaling (UCLA CHIPS). Prior to that he was an IBM Fellow. His keytechnical contributions have been the development of the world’s first SiGebase HBT, Salicide, electrical fuses, embedded DRAM and 45nm technology nodeused to make the first generation of truly low power portable devices as wellas the first commercial interposer and 3D integrated products. He has beenexploring new packaging paradigms and device innovations that may enablewafer-scale architectures, in-memory analog compute and medical engineeringapplications.   He is a fellow of IEEE, APS, iMAPS and NAI as well asa Distinguished Lecturer of IEEE EDS and EPS. He is a Distinguished Alumnus ofIIT Bombay and received the IEEE Daniel Noble Medal for emerging technologiesin 2012 and the 2020 iMAPS Daniel C. Hughes Jr Memorial award and the iMAPSdistinguished educator award in 2021.


List of publications/patents:


Upcoming Events
Day 1
09:35 – 10:05
Packaging: then, now and in the future

Packaging has evolved from the role of primarily protecting the chip to one of overall system integration of heterogeneous chiplets. An important aspect of this integration is miniaturization. Feature sizes such as substrate wiring pitch, die-to-substrate bonding pitch, and inter-die distances need to shrink in a predictable manner to approach monolithic wiring pitches, last level via pitches and IP block spacings. We refer to this as shrinking down of the package. Simultaneously, we need to increase the number of dies interconnected on the package to improve performance and functionality. We refer to this as scaling out of the package. Current approaches to this include additional levels in the packaging hierarchy with concomitant increases in complexity and cost. We need to think of new ways of flattening the packaging hierarchy by enabling substrates with finer wiring pitches and the ability to assemble dies at fine pitch at high throughput. Besides the technology and processes needed to accomplish this, there are other difficult issues that need to be addressed: these include power delivery and thermal dissipation, high bandwidth, and potentially active wired, wireless, and photonic connectors to the external world or between subsystems. Finally, to make this vision a reality a chiplet eco system needs to be developed with mechanical and electrical standards that ensure interoperability and a high level of reuse. Similarly, a comprehensive EDA approach needs to be developed that goes well beyond electrical abstraction of the system and includes among other things thermal, thermomechanical considerations, power delivery, test methodology and reliability. This is a challenging opportunity and promises to continue the trend set by Moore’s law, for system integration.

CHIPS for America R&D Office

Semiconductors, or chips, are tiny electronic devices that are integral to America’s economic and national security. These devices power tools as simple as a light switch and as complex as a fighter jet or a smartphone. Semiconductors power our consumer electronics, automobiles, data centers, critical infrastructure, and virtually all military systems. They are also essential building blocks of the technologies that will shape our future, including artificial intelligence, biotechnology, and clean energy.

While the United States remains a global leader in semiconductor design and research and development, it has fallen behind in manufacturing and now accounts for only about 10 percent of global commercial production. Today, none of the most advanced logic and memory chips—the chips that power PCs, smartphones, and supercomputers—are manufactured at commercial scale in the United States. In addition, many elements of the semiconductor supply chain are geographically concentrated, leaving them vulnerable to disruption and endangering the global economy and U.S. national security.

That’s why President Biden signed the bipartisan CHIPS and Science Act of 2022 into law. The law provides the Department of Commerce with $50 billion for a suite of programs to strengthen and revitalize the U.S. position in semiconductor research, development, and manufacturing—while also investing in American workers. CHIPS for America encompasses two offices responsible for implementing the law: The CHIPS Research and Development Office is investing $11 billion into developing a robust domestic R&D ecosystem, while the CHIPS Program Office is dedicating $39 billion to provide incentives for investment in facilities and equipment in the United States. Learn more about CHIPS for America from this video message from the Secretary of Commerce.

The U.S. Department of Commerce’s CHIPS Program Office's first funding opportunity seeks applications for projects for the construction, expansion, or modernization of commercial facilities for the fabrication of leading-edge, current-generation, and mature-node semiconductors. Through that funding opportunity, the CHIPS Program Office will soon also be accepting applications for projects for the construction, expansion, or modernization of semiconductor materials and manufacturing equipment facilities for which the capital investment equals or exceeds $300 million.

Later in 2023, the CHIPS Program Office will release a funding opportunity for R&D facilities. Altogether, these investments will be key to restoring U.S. leadership in semiconductor manufacturing, supporting good-paying jobs across the semiconductor supply chain, and advancing U.S. economic and national security.